`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:20:39 11/07/2012 
// Design Name: 
// Module Name:    DETECT_BLOCK 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DETECT_BLOCK #(parameter STR_LOG_LEN=5, STR_LEN=32, STR_TRES=0, LOG_DEPTH=9, DEPTH=416, LOG_TRIG_CYCLE=8, TRIG_CYCLE=160, TRIG_TRES=1, GAP=256, WIDTH=16, OFFSET=0)
(
	input clk_r_x,
	input clk_r_len_x,
	input rst,
	input signed[WIDTH-1:0] in_r,
	input signed[WIDTH-1:0] in_i,
	output detect
    );
	 
	 wire signed[WIDTH+WIDTH+1-1:0] square_out;
	 wire str_detect;

	 
	 wire[LOG_DEPTH-1:0] addr_corr_ram_wr;
	 wire[LOG_DEPTH-1:0] addr_corr_ram_rd_ch1;
	 wire[LOG_DEPTH-1:0] addr_corr_ram_rd_ch2;
	 wire signed[WIDTH-1:0] corr_ram_wr_r;//ctr out to ram
	 wire signed[WIDTH-1:0] corr_ram_wr_i;
	 wire signed[WIDTH-1:0] corr_ram_rd_r_ch1;//ram out to ctr
	 wire signed[WIDTH-1:0] corr_ram_rd_r_ch2;
	 wire signed[WIDTH-1:0] corr_ram_rd_i_ch1;
	 wire signed[WIDTH-1:0] corr_ram_rd_i_ch2;
	 wire wr_en;
//	 wire[WIDTH-1:0] corr_ram_r_ch1;//ctr out
//	 wire[WIDTH-1:0] corr_ram_i_ch1;
//	 wire[WIDTH-1:0] corr_ram_r_ch2;
//	 wire[WIDTH-1:0] corr_ram_i_ch2;
	 wire signed[WIDTH-1:0] tmp_ch1_r;//ALU out
	 wire signed[WIDTH-1:0] tmp_ch1_i;
	 wire signed[WIDTH-1:0] tmp_ch2_r;
	 wire signed[WIDTH-1:0] tmp_ch2_i;	 
	 
	 
	SQUARE_UNIT #(WIDTH) U_square
	(
		.clk(clk_r_x),
		.rst(rst),
		.a_r(in_r),
		.a_i(in_i),
		.out(square_out)
	);
	 
	 STRENGTH_DETECT_UNIT #(STR_LOG_LEN, STR_LEN, WIDTH+WIDTH+1, STR_TRES) U_str_detect
	(
		.clk(clk_r_x),
		.rst(rst),
		.in(square_out),
		.detect(str_detect)
    );
	
	/////////////////////////////////////
	
	CROS_CORR_RAM U_corr_ram_r_ch1(
		.clka(clk_r_len_x),
		.addra(addr_corr_ram_wr),
		.dina(corr_ram_wr_r),
		.wea(wr_en),
		.clkb(clk_r_len_x),
		.addrb(addr_corr_ram_rd_ch1),
		.doutb(corr_ram_rd_r_ch1)
		);
	
	CROS_CORR_RAM U_corr_ram_i_ch1(
		.clka(clk_r_len_x),
		.addra(addr_corr_ram_wr),
		.dina(corr_ram_wr_i),
		.wea(wr_en),
		.clkb(clk_r_len_x),
		.addrb(addr_corr_ram_rd_ch1),
		.doutb(corr_ram_rd_i_ch1)
		);
		
	CROS_CORR_RAM U_corr_ram_r_ch2(
		.clka(clk_r_len_x),
		.addra(addr_corr_ram_wr),
		.dina(corr_ram_wr_r),
		.wea(wr_en),
		.clkb(clk_r_len_x),
		.addrb(addr_corr_ram_rd_ch2),
		.doutb(corr_ram_rd_r_ch2)
		);
	
	CROS_CORR_RAM U_corr_ram_i_ch2(
		.clka(clk_r_len_x),
		.addra(addr_corr_ram_wr),
		.dina(corr_ram_wr_i),
		.wea(wr_en),
		.clkb(clk_r_len_x),
		.addrb(addr_corr_ram_rd_ch2),
		.doutb(corr_ram_rd_i_ch2)
		);
		
		
	MEM_WR #(LOG_DEPTH, DEPTH, WIDTH) U_corr_ram_wr_dual
	(
		.clk(clk_r_x),
		.rst(rst),
		.in_r(in_r),
		.in_i(in_i),
		.out_r(corr_ram_wr_r),
		.out_i(corr_ram_wr_i),
		.addr(addr_corr_ram_wr),
		.wr_en(wr_en)
    );


	MEM_RD_DUAL #(LOG_DEPTH, DEPTH, LOG_TRIG_CYCLE, TRIG_CYCLE, WIDTH, OFFSET, GAP) U_corr_ram_rd_dual
	(
		.clk(clk_r_len_x),
		.rst(rst),
		.ch1_to_rd_r(corr_ram_rd_r_ch1),
		.ch1_to_rd_i(corr_ram_rd_i_ch1),
		.ch2_to_rd_r(corr_ram_rd_r_ch2),
		.ch2_to_rd_i(corr_ram_rd_i_ch2),
		.addr_wr(addr_corr_ram_wr),
		.ch1_rd_r(tmp_ch1_r),
		.ch1_rd_i(tmp_ch1_i),
		.ch2_rd_r(tmp_ch2_r),
		.ch2_rd_i(tmp_ch2_i),
		.addr_rd_ch1(addr_corr_ram_rd_ch1),
		.addr_rd_ch2(addr_corr_ram_rd_ch2)
		);
		
		
	TRIG_UNIT #(LOG_TRIG_CYCLE, TRIG_CYCLE, WIDTH, TRIG_TRES) U_trig
	(
		.clk_r_x(clk_r_x),
		.clk_r_len_x(clk_r_len_x),
		.rst(rst),
		.strength_detect(str_detect),
		.ch1_r(tmp_ch1_r),
		.ch1_i(tmp_ch1_i),
		.ch2_r(tmp_ch2_r),
		.ch2_i(tmp_ch2_i),
		.trig(detect)
		);

endmodule
